Semiconductor device with bipolar transistor device

ABSTRACT

A single transistor device is configured of a plurality of transistor cells divided and arranged in a plurality of blocks. Corresponding to the blocks a plurality of bias current supply circuits are arranged, respectively, to supply the blocks with individual bias currents, respectively. The bias current supply circuits each have a transistor with a bias condition set to decrease its ability to drive current as the corresponding bias current increases. Thus a negative feedback can be given to an increase in bias current attributed to thermal unevenness.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductor devicesand particularly to those including a bipolar transistor deviceconfigured of transistor cells arranged in a matrix.

[0003] 2. Description of the Background Art

[0004] Power amplifiers for mobile communications currently, widely usedinclude monolithic microwave integrated circuits (MMICs), hybridintegrated circuits (hybrid ICs), multitip modules and the like. Thesemodules have an amplifying element in the form of a GaAs-metalsemiconductor field effect transistor (GaAs-MESFET), a high electronmobility transistor (HEMT), a hetero-junction bipolar transistor (HBT)or the like.

[0005] Particularly, a hetero-junction bipolar transistor (hereinafteralso simply referred to as an HBT) formed on a GaAs substrate, a Sisubstrate or the like is expected to serve as a future power element formobile communications as it is more advantageous than conventional fieldeffect transistors (FETs), as described below:

[0006] (1) operable by a single power supply as it does not require anegative gate bias voltage;

[0007] (2) capable of turning on/off without having an analogue switchon its drain side, as in a Si-metal oxide semiconductor FET (Si-MOSFET);and

[0008] (3) having a high output power density, thus capable of providinga defined output if it is reduced in size as compared to FET poweramplifiers.

[0009] As such features of the HBT attract attention, an HBT poweramplifier is also being applied for example to a 2 W-4 W, high-outputmobile telephone, such as the European Global System for MobileCommunications (European GSM), a currently most widely used, 900 MHzband mobile telephone system mainly employing a Si-MOSFET.

[0010] A power amplifier employs a transistor device generallyconfigured of a plurality of transistor cells arranged on asemiconductor substrate in rows and columns. Hereinafter such aconfiguration will also be referred to as a multi transistor cellconfiguration.

[0011]FIG. 14 is a circuit diagram showing a configuration of a bipolartransistor device having a multi transistor cell configuration.

[0012] With reference to FIG. 14, a plurality of transistor cellsTr11-Trmn arranged in m rows and n columns in effect operate as a singlebipolar transistor device TR, wherein m and n are each a natural number.

[0013] Corresponding to the rows of transistor cells, local base linesLBL1-LBLm and local collector lines LCL1-LCLm are arranged,respectively. Hereinafter, local base lines LBL1-LBLm and localcollector lines LCL1-LCLm will generally be referred to as a local baseline LBL and a local collector line LCL, respectively.

[0014] Each transistor cell has its base and collector regionselectrically coupled with its corresponding row's local base andcollector lines LBL and LCL, respectively.

[0015] Local base lines LBL1-LBLm are each electrically coupled with acommon base line CBL. On common base line CBL, a bias current Ibssupplied from a bias supply circuit (not shown) is superimposed on an RFsignal input to a base terminal Tb.

[0016] Local collector lines LCL1-LCLm are each electrically coupledwith a common collector line CCL. Furthermore, each transistor cell hasits emitter region electrically coupled with a ground voltage Vss toprovide a so-called emitter-grounding.

[0017] Transistor device TR applied to a power amplifier receives aradio-frequency input (an RF signal input) at base terminal Tb coupledwith common base line CBL and outputs an amplified, radio-frequencyoutput (RF signal output) at collector terminal Tc coupled with commoncollector line CCL.

[0018] Corresponding to transistor cells Tr11-Trmn, base ballastresistors Rb 11-Rbmn and emitter ballast resistors Re 11-Remn areprovided, respectively. A ballast resistor is generally used to preventa bipolar transistor device having a multi transistor cell configurationfrom having an uneven collector current attributable for example to anuneven heat distribution caused by heat generation.

[0019] More specifically, each base ballast resistor and each emitterballast resistor when their respective transistor cell operates give anegative feedback to a base current and an emitter current,respectively. Thus they act to eliminate a variation in current betweentransistor cells to provide a uniform current. This can prevent aspecific transistor cell from intensively receiving current and thusprevent the transistor from being thermally destroyed.

[0020]FIG. 15 is a conceptual view showing a layout of a bipolartransistor device having a multi transistor cell configuration.

[0021]FIG. 15 shows a bipolar transistor device TR configured oftransistor cells Tr11-Tr67 arranged in six rows and seven columns by wayof example. Transistor cells Tr11-Tr67 are grouped into blocks BLK1-BLK3each formed of two rows of transistor cells.

[0022] Corresponding to blocks BLK1-BLK3, local base lines LBL1-LBL3 arearranged, respectively. Each transistor cell has its base regionelectrically coupled with its corresponding local base line LBL via abase ballast resistor. In FIG. 15, the arrangement of a base ballastresistor Rbl2 for transistor cell Trl2 is shown representatively.

[0023] Local base lines LBL1-LBL3 are each coupled with common base lineCBL. Common base line CBL passes bias current Ibs and also receives anRF signal input.

[0024] Each transistor cell has its collector region coupled with arespective one of local collector lines LCL1 a and LCL1 b to LCL3 a andLCL3 b provided for their respective rows of transistor cells. Localcollector lines LCL1 a and LCL1 b to LCL3 a and LCL3 b are each coupledwith collector terminal Tc outputting an amplified RF signal.

[0025] Similarly, each transistor cell has its emitter regionelectrically coupled via an emitter ballast resistor (not shown) withcommon emitter line CEL coupled with ground voltage Vss.

[0026]FIGS. 16A and 16B are graphs each showing a distribution of a basecurrent in a bipolar transistor device having a multi transistor cellconfiguration.

[0027] With reference to FIG. 16A, if the FIG. 15 bipolar transistor TRhas a small base current, thermal, mutual interference between theblocks and that between the transistor cells only have a small effectand blocks BLK1-BLK3 have their respective base currents Ib1-Ib3 thatare substantially uniform and thus provide a standard amount of currentI1.

[0028] In contrast, as shown in FIG. 16B, if base current in totalincreases and thermal, mutual interference between the blocks and thatbetween the transistor cells are no longer negligible, the operatingtemperature of transistor cells closer to the center of the transistorincreases higher than that of peripheral transistor cells and thetransistor cells with their operating temperature increased thus have anincreased collector current.

[0029] In the FIG. 15 exemplary layout, base current Ib2 for block BLK2closer to the center and thus greater in temperature elevation wouldhave an amount of current I3 (wherein I3>>I1) larger than an amount ofcurrent I2 of base currents Ib1 and Ib3 for the other blocks (whereinI2<I1). Thus a specific block receives an intensive current.

[0030] Furthermore even within a single block a transistor cell closerto the center of the block has its operating temperature increased,resulting in a further uneven temperature profile. For example in FIG.15 transistor cells Tr34 and Tr44 would have an operating temperaturethat most readily increase.

[0031] Thus, an uneven operating-temperature profile results in anuneven base current (or an uneven collector current), which in turnresults in an unevenness between the blocks and further develops to acurrent intensively flowing in a block through a specific transistorcell, and ultimately, approximately more than 90% of the base current(collector current) flowing through the entire transistor device TRwould intensively flow to the specific transistor cell.

[0032] Such a significantly intensive current results in the transistorcell having a current-amplification rate β (collector current/basecurrent) significantly reduced due to heat generation. As such, such anintensive current, as seen in the transistor's Ic (collectorcurrent)-Vce (voltage between collector and emitter) characteristic, isobserved as a phenomenon with collector current Ic rapidly decreasing asbase current Ib increases even if voltage Vce is constant. Such aphenomenon is also referred to as a gain reduction attributed to anintensive current.

[0033]FIG. 17 represents an HBT device's typical Ic-Vce characteristicand load curve in its power amplification operation.

[0034] In FIG. 17 the horizontal axis represents collector-emittervoltage Vce of an HBT corresponding to a transistor cell and thevertical axis represents collector current Ic thereof. These Vce-Iccharacteristics are plotted in FIG. 17 with base current Ib serving as aparameter.

[0035] With reference to FIG. 17, if collector-emitter voltage Vce isincreased while a constant base current is applied, collector lossincreases and collector current Ic rapidly decreases in a region.Hereinafter such a region with a rapid reduction in collector current Icwill also be referred to as a “collapse region.”

[0036] If collector-emitter voltage Vce has a constant level, such acollapse region expands as base current Ib increases.

[0037] A load curve CV1 represents a load curve provided at a matchedload resistance (50 Ω), or when a standard bias is applied, and the loadcurve has a highly resistive, efficient locus with a bias point A1serving as its center. Thus, power amplification operation can beperformed as desired.

[0038] In typical mobile telephone systems including Japanese mobiletelephone systems a variation in output impedance of an antenna elementis not linked directly to a variation in load of a power amplifier andan isolator is thus employed therebetween. In contrast, the GSMapplication as described above is significantly oriented tominiaturization and reduction in output loss. Accordingly it is notprovided with an isolator. As such, depending on a load condition of theantenna, the power amplifier with an HBT applied thereto would have asignificantly varying load impedance.

[0039] A load curve CV2 represents a load curve provided when a poweramplifier has a significantly varying load impedance, as describedabove. In this case, a significant reflection occurs and the load curvewould expand significantly.

[0040] If in this case a transistor cell has a base current increased byan uneven operating temperature, the transistor cell would have areduced margin for load impedance variation that is applied to avoidoperation in the collapse region. In other words, for a given loadimpedance variation a transistor cell having a base current increased byan intensive current would more readily operate in the collapse region.

[0041] FIGS. 18A-18C represent an amplification operation of a typicalpower amplifier in a mobile telephone.

[0042]FIG. 18A represents a waveform of a signal input to a poweramplifier employed in a mobile telephone. The signal input is a voltagesignal in a pulse having an amplitude Vp.

[0043]FIG. 18B represents a waveform of an output provided when thepower amplifier operates in a standard load condition as represented bythe FIG. 17 load curve CV1. In this condition, the power amplifierexhibits a normal amplification characteristic and a pulsed, outputsignal has a constant power amplification.

[0044]FIG. 18C represents a waveform of an output provided when atransistor in the power amplifier operates in a collapse region, asshown in FIG. 17 by load curve CV2. In such a case, while a pulsedsignal is amplified a single pulse would have therein a reduction inoutput power. As such, a pulsed signal input is inaccurately amplifiedand a single pulse would have therein a variation in output power. Thismay prevent normal communication.

[0045] Thus if a specific transistor cell receives an intensive currentattributed to thermal unevenness the entire transistor device might havean impaired amplification characteristic. Furthermore, if such anintensive current is further intensified, not only is an amplificationcharacteristic impaired but the transistor device may be destroyed.

[0046] Such disadvantages attributable to intensive current are commonamong bipolar transistor devices having multi transistor configuration.A GaAs substrate, on which an HBT is formed, has a high thermalresistance and once heat is generated it is hardly released therefrom,readily resulting in a thermally uneven profile across transistor cells.Thus, power amplifiers employing an HBT would more significantly suffersuch disadvantages as described above.

[0047] Intensive current attributable to thermal unevenness can beprevented to some extent by providing a ballast resistor previouslydescribed. If ballast resistors are uniformly provided, however, theyhardly effectively reduce an intensive current flowing to a specificblock before a specific transistor cell receives an intensive current.

[0048] Transistor cells arranged in rows and columns can have a moreuniform thermal distribution thereacross if a smaller number oftransistor cells are arranged closer to the center of the transistordevice and a larger number of transistor cells are arranged closer tothe periphery thereof to alleviate heat generation and thermal effect atthe center thereof or if ballast resistors closer to the center thereof,which generates heat intensively, are adapted to have a large value ofresistance and those closer to the periphery thereof, which is free fromsignificant temperature elevation, are adapted to have a small value ofresistance.

[0049] Such adjustments, however, require a long period of time tooptimize the number of transistor cells and the values in resistance ofballast resistors and they would in effect be hard to achieve.

SUMMARY OF THE INVENTION

[0050] The present invention contemplates providing a semiconductordevice including a bipolar transistor device having a so-calledmultitransistor configuration with a circuit configuration capable ofpreventing a specific transistor cell from receiving an intensivecurrent, to enable the transistor device to provide a reliableamplification operation and also to reduce the possibility of the devicebeing destroyed.

[0051] Briefly speaking, the semiconductor device includes a pluralityof transistor cells, a plurality of first lines, a plurality of secondlines, a reference voltage line and a plurality of bias current supplycircuits. The plurality of transistor cells are divided and thusarranged in a plurality of blocks to form the bipolar transistor device.The plurality of first lines are provided for the plurality of blocks,respectively, and each electrically coupled with the base region of eachtransistor cell of the corresponding block. The plurality of secondlines are provided for the plurality of blocks, respectively, and eachelectrically coupled with one of the collector and emitter regions ofeach transistor cell of the corresponding block. The reference voltageline is electrically coupled with the other of the collector and emitterregions of each of the plurality of transistor cells. The plurality ofbias current supply circuits are provided for the plurality of blocks,respectively, and each supplies a bias current to a corresponding one ofthe plurality of first lines. If the bias current increases, each biascurrent supply circuit reduces an amount of bias current to be supplied.

[0052] Thus a main advantage of the present invention is that bysupplying a bias current via a bias current supply circuit arrangedindividually for each block and capable of giving a negative feedback toan increase in bias current, a bias current for a block receiving anintensive current attributed to thermal unevenness can be controlled toprevent a specific block from receiving an intensive current before aspecific transistor cell receives an intensive current. Thus thetransistor device can have a steady amplification characteristic andalso be free from destruction.

[0053] In the present invention in another aspect the semiconductordevice includes a plurality of transistor cells, a plurality of firstlines, a plurality of second lines, a reference voltage line and aplurality of feedback circuits. The plurality of transistor cells aredivided and thus arranged in a plurality of blocks to form the bipolartransistor device. The plurality of first lines are provided for theplurality of blocks, respectively, and each electrically coupled withthe base region of each transistor cell of the corresponding block. Theplurality of second lines are provided for the plurality of blocks,respectively, and each electrically coupled with one of the collectorand emitter regions of each transistor cell of the corresponding block.The reference voltage line is electrically coupled with the other of thecollector and emitter regions of each of the plurality of transistorcells. The plurality of feedback circuits are provided for the pluralityof blocks, respectively, and each electrically coupling a correspondingone of the plurality of second lines and a predetermined internal nodetogether if the corresponding second line and the internal node havetherebetween a voltage difference exceeding a predetermined level ofvoltage.

[0054] Thus, the feedback circuits each arranged for a block of multipletransistor cells can maintain a predetermined level of voltage or lessof one of collector and emitter regions that is not coupled with thereference voltage line. As such, each transistor cell can be operatedavoiding a region having a gain significantly reduced. Thus, eachtransistor cell can be free of operation under a severe conditionattributable for example to intensive current and the transistor devicecan thus have a steady amplification characteristic and also be freefrom destruction.

[0055] In the present invention in still another aspect a semiconductordevice provided on a semiconductor chip includes a plurality of bipolartransistor devices amplifying a signal in phases. The plurality ofbipolar transistor devices are arranged on the semiconductor chip, abipolar transistor device of a stage preceding another stage arranged ata location experiencing a greater temperature elevation than anotherlocation.

[0056] As such, of the plurality of transistor devices amplifying asignal in phase, transistor devices of subsequent stages, accommodatinghigher levels of power and thus readily generating heat, can besuccessively arranged at locations experiencing lower levels oftemperature elevation. As such, if temperature elevation causesintensive current, a transistor device accommodating a high level ofpower can receive reduced power. This allows each transistor device toprovide reliable amplification and can also reduce the possibility ofthe device being destroyed.

[0057] In the present invention in still another aspect a semiconductordevice provided on a semiconductor chip includes a plurality oftransistor cells, a plurality of first lines, a plurality of secondlines, a reference voltage line, a bias current supply circuit, and aplurality of ballast resistors. The plurality of transistor cells aredivided and thus arranged in a plurality of blocks to form the bipolartransistor device. The plurality of first lines are provided for theplurality of blocks, respectively, and each electrically coupled withthe base region of each transistor cell of the corresponding block. Theplurality of second lines are provided for the plurality of blocks,respectively, and each electrically coupled with one of the collectorand emitter regions of each transistor cell of the corresponding block.The reference voltage line is electrically coupled with the other of thecollector and emitter regions of each of the plurality of transistorcells. The bias supply circuit is shared by the plurality of blocks andsupplies each first line with a bias current. The plurality of ballastresistors are provided for the plurality of blocks, respectively, andeach electrically coupled between the bias supply circuit and acorresponding one of the plurality of first lines. The plurality ofballast resistors are arranged on the semiconductor chip at a locationexperiencing a greater temperature elevation than a location having theplurality of transistor cells arranged therein.

[0058] For each block of multiple transistor cells configuring thetransistor device a ballast resistor can be arranged on thesemiconductor chip at a location experiencing a high temperatureelevation, to give a negative feedback to an increase of a bias currentfor a specific block. This can efficiently reduce an intensive currentflowing to a specific transistor cell that is attributed to thermalunevenness and the transistor device can thus have a steadyamplification characteristic and also be free from destruction.

[0059] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In the drawings:

[0061]FIG. 1 is a circuit diagram showing a typical configuration of anGSM power amplifier;

[0062]FIG. 2 is a circuit diagram showing a configuration of a bipolartransistor device in a first embodiment of the present invention;

[0063]FIG. 3 is a conceptual view showing by way of example a layout ofa bipolar transistor device of the first embodiment;

[0064]FIG. 4 is a circuit diagram showing a configuration of a bipolartransistor in a second embodiment of the present invention;

[0065]FIG. 5 is a circuit diagram showing a configuration of a bipolartransistor device in an exemplary variation of the second embodiment;

[0066]FIG. 6 is a circuit diagram showing a configuration of a bipolartransistor device in a third embodiment of the present invention;

[0067]FIGS. 7A and 7B are circuit diagrams each showing anotherexemplary configuration of an active feedback circuit;

[0068]FIG. 8 is a conceptual view showing a first exemplary arrangementof an active feedback circuit AFB;

[0069]FIG. 9 is a conceptual view showing a second exemplary arrangementof active feedback circuit AFB;

[0070]FIG. 10 is a circuit diagram showing a configuration of a bipolartransistor device in a first exemplary variation of the thirdembodiment;

[0071]FIG. 11 is a circuit diagram showing a configuration of a bipolartransistor device in a second exemplary variation of the thirdembodiment;

[0072]FIG. 12 is a circuit diagram showing a configuration of atransistor device in a third exemplary variation of the thirdembodiment;

[0073]FIG. 13 is a conceptual view for illustrating an arrangement of atransistor device in a fourth embodiment of the present invention;

[0074]FIG. 14 is a circuit diagram showing a configuration of a bipolartransistor device having a multi transistor cell configuration;

[0075]FIG. 15 is a conceptual view showing a layout of a bipolartransistor device having a multi transistor cell configuration;

[0076]FIGS. 16A and 16B are each a graph representing a profile in basecurrent of the bipolar transistor device having the multi transistorcell configuration as shown in FIG. 15;

[0077]FIG. 17 represents an HBT device's typical Ic-Vce characteristicand load curve in power amplification operation; and

[0078] FIGS. 18A-18C represent an amplification operation of a typicalpower amplifier employed in a mobile telephone.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] Hereinafter the embodiments of the present invention will bedescribed in detail with reference to the drawings.

[0080] First Embodiment

[0081]FIG. 1 shows a configuration of a typical GSM power amplifier 1exemplarily representing a semiconductor device including a bipolartransistor device of an embodiment of the present invention.

[0082] As shown in FIG. 1, power amplifier 1 is provided on a GaAssubstrate 2. Power amplifier 1 has an input terminal Tin receiving asignal input, bipolar transistor devices (hereinafter also simplyreferred to as transistors) Q1, Q2 and Q3 provided to amplify power, andan output terminal Tout outputting an amplified signal. For the GSMapplication, these bipolar transistor devices are HBTs, although notethat the present invention is directed to a configuration of a bipolartransistor device having a multi transistor cell configuration and itsapplication is not limited to HBTs.

[0083] While FIG. 1 shows that an HBT can be provided on a GaAssubstrate by way of example, it may be provided on a substrate formed ofa material other than GaAs.

[0084] With reference to FIG. 1, three amplifying transistor devicesQ1-Q3 are used to provide a 3-phased amplification operation.Corresponding to transistors Q1, Q2 and Q3, bias circuits 4, 5 and 6 areprovided, respectively. A voltage Vcc is supplied as a power supplyvoltage for the bias circuits. In response to the level of a controlvoltage Vpc applied, bias circuits 4, 5 and 6 control an amount of abias current supplied to transistors Q1, Q2 and Q3 at their baseregions. Bias circuits 4, 5 and 6 feed a bias current to transistors Q1,Q2 and Q3 via base bias resistors Rb1, Rb2 and Rb3.

[0085] In FIG. 1, transistor Q3, the transistor in the final stage,receives a bias current particularly labeled Ibs. Bias current Ibs issupplied to an input node Nin, which also receives an RF inputcorresponding to a radio-frequency signal amplified by transistor Q2,the transistor of the immediately preceding stage.

[0086] Voltages Vc1, Vc2 and Vc3 correspond to collector bias voltagesof transistors Q1, Q2 and Q3. Transistors Q1, Q2 and Q3 each provideamplification via an RC feedback circuit, since an HBT power amplifierhas a high low-frequency gain and provides low-frequency oscillationmore readily than an FET power amplifier. In FIG. 1, sets of (Rf1, Cf1),(Rf2, Cf2), (Rf3, Cf3) each configure an RC feedback circuit for thetransistor of a stage.

[0087] Furthermore, reference characters Cin1, C1, C2, C3 denotecapacitors and Ra1-Ra3, Rs1, Rb11-Rb32, Rs1-Rs3, R1-R3, Rc3 denoteresistors. Between an output node Nout corresponding to a collectorterminal of the final-stage transistor Q3 and output terminal Tout thereare arranged microwave lines Lo1-Lo5 and capacitors Co1-Co3.

[0088] The FIG. 1 transistors Q1-Q3 are each arranged on GaAs substrate2 in a multi transistor cell configuration. Each transistor can besimilarly configured and hereinafter the last-stage transistor Q3configuration will be representatively described.

[0089] With reference to FIG. 2, transistor Q3, a bipolar transistor ofthe first embodiment, is formed of transistor cells Tr11-Trmn arrangedin m rows and n columns. The transistor cells belonging to a single rowform a single block. Transistor cells Tr11-Trmn are divided and thusarranged in blocks BLK1-BLKm.

[0090] Corresponding to blocks BLK1-BLKm, local base lines LBL1-LBLm andlocal collector lines LCL1-LCLm are arranged, respectively. Eachtransistor cell has its base and collector regions electrically coupledwith local base and collector lines LBL and LCL, respectively, of itsrespective block.

[0091] Each local base line LBL is electrically coupled with a commonbase line CBL receiving a bias current Ibs from bias circuit 6 and an RFinput transmitted from transistor Q2 to input node Nin.

[0092] Local collector lines LCL1-LCLm are each coupled with a commoncollector line CCL coupled with an output node Nout. Each transistorcell has its emitter region electrically coupled with a ground line GNL(a ground voltage Vss) to provide emitter-grounding.

[0093] Similarly as described with reference to FIG. 14, for eachtransistor cell a base ballast resistor and an emitter ballast resistorare arranged. For example, for transistor cell Tr11 a base ballastresistor Rb11 and an emitter ballast resistor Re11 are arranged.Furthermore, corresponding to blocks BLK1-BLKm, ballast resistorsRbb1-Rbbm are provided, respectively, each electrically coupled betweencommon base line CBL and a respective one of local base lines LBL1-LBLm.

[0094] Since each block is further provided with a respective one ofballast resistors Rbb1-Rbbm, a negative feedback can be given to avariation between base currents Ib1-Ibm for their respective blocks toprovide a uniform current. As has been described above, in amultitransistor configuration a specific block initially receives anintensive current and in the specific block receiving the intensivecurrent a specific transistor cell subsequently receives an intensivecurrent. In the present embodiment, before a specific transistor cellreceives an intensive current a negative feedback can be given to avariation in base current between blocks to reduce an intensive currentflowing to the specific block, to effectively prevent the specifictransistor cell from receiving an intensive current.

[0095] This can stabilize an amplification characteristic of thetransistor device and prevent destruction of the device.

[0096]FIG. 3 shows an exemplary layout of a bipolar transistor device ofthe first embodiment.

[0097] As shown in FIG. 3, a bipolar transistor device is shown,exemplarily configured of transistor cells Tr11-Tr46 arranged in fourrows and six columns.

[0098] The transistor cells arranged avoiding the center of the device,a portion experiencing a most significant temperature elevation. At thecenter of the device are arranged ballast resistors Rbb1-Rbb4.

[0099] Transistor cells Tr11-Tr46 are divided into four blocks BLK1-BLK4each including a predetermined number of rows (in FIG. 3, two rows) oftransistor cells divided by the center region having the ballastresistors.

[0100] Corresponding to blocks BLK1-BLK4, local base lines LBL1-LBL4 arearranged, respectively. Each transistor cell has its base regionelectrically coupled with a respective local base line LBL via a baseballast resistor. In FIG. 3, an arrangement of a base ballast resistorRbl2 for transistor cell Trl2 is representatively shown.

[0101] Local base lines LBL1-LBL4 are coupled with a common base lineCBL via ballast resistors Rbb1-Rbb4 provided corresponding to blocksBLK1-BLK4, respectively. Common base line CBL receives bias current Ibsand an RF signal input.

[0102] Each transistor cell has its collector region coupled with acorresponding one of local collector lines LCL1-LCL4 respectivelyprovided for the rows of transistor cells. Local collector linesLCL1-LCL4 are each coupled with output node Nout corresponding to acollector terminal of the bipolar transistor device that outputs anamplified RF signal output.

[0103] Each transistor cell has its emitter region electrically coupledvia an emitter ballast resistor (not shown) with a common emitter lineCEL coupled with a ground line GNL.

[0104] Ballast resistors Rbb1-Rbb4 can reduce unevenness of basecurrents Ib 1-Ib4 flowing through local base lines LBL1-LBL4,respectively, to prevent a specific block from receiving an intensivecurrent. Thus a specific transistor cell can be prevented in advancefrom receiving an intensive current.

[0105] Ballast resistors Rbb1-Rbb4, respectively provided for blocksBLK1-BLK4 divided in rows and columns, are arranged in the regionsbetween the blocks adjacent in the direction of the rows, i.e., theregion between blocks BLK1 and BLK3 and that between blocks BLK2 andBLK4. These regions are located closer to the center of the device andthus experience a temperature elevation greater than the regions havingthe transistor cells arranged therein.

[0106] It should be noted that as a variation of the FIG. 3configuration, ballast resistors Rbb1-Rbb4 can be arranged in theregions between the blocks adjacent in the direction of the columns,i.e., the region between blocks BLK1 and BLK2 and that between blocksBLK3 and BLK4.

[0107] Thus transistor cells are arranged in regions other than thecenter region experiencing a most significant temperature elevation.This can further effectively prevent a specific transistor cell fromreceiving an intensive current. Thus, the transistor device can have afurther stable amplification characteristic and it can also further befree from destruction.

[0108] Second Embodiment

[0109]FIG. 4 shows a configuration of a bipolar transistor device in asecond embodiment of the present invention.

[0110] As shown in FIG. 4, a plurality of transistor cells Tr11-Trmnarranged in m rows and n columns are divided into blocks eachcorresponding to a row of transistor cells. Thus, transistor cellsTr11-Trmn are divided and thus arranged in blocks BLK1-BLKm. For eachblock, a local base line LBL and a local collector line LCL arearranged.

[0111] In the second embodiment, common bias circuit 6 shown in FIG. 1is replaced by individual bias current supply circuits 10-1 to 10-m forblocks BLK1-BLKm, respectively. Between bias current supply circuits10-1 to 10-m and local base lines LBL1-LBLm there exist high impedancetransmission lines RFC1-RFCm arranged to separate the base regions ofthe transistor cells of each block and the bias supply circuits fromeach other in terms of radio frequency. The high impedance transmissionline can be a radio frequency inductance element.

[0112] Bias current supply circuits 10-1 to 10-m supply bias currentsIb1-Ibm which are in turn fed on local base lines LBL1-LBLm. An RF inputis in turn transmitted via a filter circuit 15 onto each of local baselines LBL1-LBLm.

[0113] Filter circuit 15 includes a capacitor C passing the RF input,resistors Rf1-Rfm each coupled in series between input node Nin and arespective one of local base lines Rf1-Rfm, and resistors Rfl2, Rf23, .. . , Rfm1 coupled between each coupled between two of local base linesRf1-Rfm. Filter circuit 15 allows local base lines Rf1-Rfm to eachreceive an alternate-current component of the RF input received at inputnode Nin.

[0114] The bias current supply circuits are configured, as describedhereinafter. Since bias current supply circuits 10-1 to 10-n aresimilarly configured, the configuration of bias current supply circuit10-1 will be representatively described.

[0115] Bias current supply circuit 10-1 includes a transistor Trb1provided to control an amount of bias current, a collector load resistorRcb1 coupled between power supply voltage Vcc and a collector terminalof transistor Trb1, and an emitter resistance Reb1 coupled betweentransistor Trb1 and ground voltage Vss. Bias current supply circuit 10-1is an emitter-follower bias circuit. Transistor Trb1 has its base regionreceiving control voltage Vpc for controlling a bias current in level.

[0116] In bias current supply circuit 10-1, collector load resistanceRcb1 serves as a bias adjusting portion reducing transistor Trb1'sability to drive current or its current-amplification rate as basecurrent Ib1 increases. The current-amplification rate of transistor Trb1is a collector current of the transistor divided by a base current ofthe transistor. As bias current Ib1 increases, with the transistor'scollector current Icb1 increasing, collector load resistance Rcb1experiences an increased voltage drop. Thus, transistor Trb1 has areduced emitter-collector voltage.

[0117] In particular, if a bias condition is set to allow transistorTrb1 to transition, for bias current Ib1 exceeding a predeterminedlevel, from an active-region operation to a saturation-region operationin response to a voltage drop caused by collector load resistance Rcb1,then the transistor Trb1 ability to drive current can be reduced tolimit bias current Ib1. In other words, a negative feedback can be givento an increase of bias current Ib1 attributed to thermal unevenness.

[0118] Thus a bias current of a block receiving an intensive currentattributed to thermal unevenness can be limited to provide a uniformbase current for blocks. As such before a specific transistor cellreceives an intensive current a specific block can be prevented fromreceiving an intensive current. Thus, uneven operation can be reduced.

[0119] Thus the transistor device can have a steady amplificationcharacteristic and it can also be free from destruction.

[0120] Variation of Second Embodiment

[0121]FIG. 5 shows a configuration of a bipolar transistor device as avariation of the second embodiment.

[0122] As compared with FIG. 4, FIG. 5 shows the variation of the secondembodiment with high impedance transmission lines RFC1-RFCm replacedwith resistors Rbb1-Rbbm. Similar to the FIG. 4 high impedancetransmission lines RFC1-RFCm, resistors Rbb1-Rbbm attenuate a radiofrequency component of bias currents Ib1-Ibm output from bias currentsupply circuits 10-1 to 10-m. Resistors Rbb1-Rbbm also serve as ballastresistors each arranged for a block, as shown in FIG. 2, forcompensating for unevenness in base current between blocks BLK1-BLKm.

[0123] Furthermore, bias current supply circuits 10-1 to 10-m are alsoreplaced by bias current supply circuits 11-1 to 11-m formed of asmaller number of components than bias current supply circuits 10-1 to10-m. Bias current supply circuits 11-1 to 11-m are each different inconfiguration from bias current supply circuits 10-1 to 10-m in thatcollector load resistances Rcb1-Rcbm are dispensed with. Collector loadresistances Rcb1-Rcbm can be dispensed with because at resistorsRbb1-Rbbm, serving as the ballast resistors for blocks BLK1-BLKm,respectively, bias currents Ib1-Ibm can cause a voltage drop and thuslimit a base current for a block receiving an intensive current.

[0124] Thus the variation of the second embodiment can provide aconfiguration having a bias current supply circuit formed of a reducednumber of components. The remainder of the configuration and operationwill not be described as it is similar to that of the second embodimentshown in FIG. 4.

[0125] Thus as well as in the second embodiment a specific transistorcell can be free from an intensive current and the transistor device canthus have a steady amplification characteristic and it can also be freefrom destruction.

[0126] Third Embodiment

[0127]FIG. 6 shows a configuration of a bipolar transistor device in athird embodiment of the present invention.

[0128] As shown in FIG. 6, transistor cells Tr11-Trmn arranged in m rowsand n columns form blocks BLK1-BLKm each corresponding to a row oftransistor cells. Corresponding to blocks BLK1-BLKm, local base linesLBL1-LBLm and local collector lines LCL1-LCLm are arranged,respectively.

[0129] Local base lines are coupled with common base line CBL receivingbias current Ibs from common bias circuit 6. Local collector linesLCL1-LCLm are coupled via common collector line CCL with output nodeNout outputting an amplified RF signal.

[0130] An RF signal input is in turn transmitted via a transistor Tr2 toan intermediate node Nr. Transistor Tr2 has its collector region coupledwith a power supply voltage Vc2 via a microwave line. Transistor Tr2 hasits base received the RF signal input. Transistor Tr2 has its emitterregions coupled with ground voltage Vss. Input node Nr has a voltagelevel transmitted to each of local base lines LBL1-LBLm via filtercircuit 15 similar to that shown in FIG. 14.

[0131] The third embodiment provides a configuration having blocksBLK1-BLKm provided with active feedback circuits AFB1-AFBm,respectively. Active feedback circuits AFB1-AFBm are identical inconfiguration and active feedback circuit AFB1 will be describedrepresentatively. Hereinafter, active feedback circuits AFB1-AFBm willalso generally be referred to simply as an active feedback circuit AFB.

[0132] Active feedback circuit AFB1 includes a transistor cell Tra1electrically coupled between local collector line LCL1 and intermediatenode Nr, a resistor Rfba1 coupled between local collector line LCL1 andtransistor cell Tra1 at the base terminal, and a resistor Rfbb1 coupledbetween the base terminal of transistor cell Tra1 and input node Nr. Theactive feedback circuits include transistor cells Tra1-Tram, which willalso generally be referred to simply as a transistor cell Tra.

[0133] Each active feedback circuit AFB is connected to internal nodeNr, which is only required to be a route for interconnection between thecollector terminal of transistor Tr2 corresponding to a preceding stageand local base lines LBL1-LBLm each corresponding to a block includingthe active feedback circuit. As such, intermediate node Nr, connectedwith any active feedback circuit AFBi of the plurality of activefeedback circuits AFB1-AFBm, may be a node with resistors Rf1-Rfm and acapacitor C connected thereto (i.e., a node Nin in FIGS. 5 and 6),wherein i is a natural number from one to m. Alternatively, intermediatenode Nr with active feedback circuit AFBi connected thereto may be acorresponding local base line LBL1.

[0134] Resistors Rfba1 and Rfbb1 allow transistor cell Tra1 to have abase-emitter voltage Vbe depending on a voltage difference ΔV betweenlocal collector line LCL1 and intermediate node Nr, set as representedby the following expression (1):

Vbe=ΔV×Rfbb 1/(Rfba 1+Rfbb 1)  —(1)

[0135] As such, transistor cell Tra1 for active feedback turns on undera condition expressed with a collector-emitter voltage Vce correspondingto voltage difference ΔV between local collector line LCL1 andintermediate node Nr, as represented by the following equation (2):

Vce>Von×(1+Rfba 1/Rfbb 1)  (2)

[0136] wherein Von represents the ON voltage of the base-emitter voltageof transistor cell Tra1.

[0137] The other active feedback circuits AFBs are similarly configured,each arranged between a corresponding local collector line LCL andintermediate node Nr.

[0138] If between local collector line LCL and intermediate node Nrthere is a voltage exceeding a predetermined level then active feedbackcircuit AFB electrically couples local collector line LCL andintermediate node Nr together at least in alternate current. If betweenlocal collector line LCL and intermediate node Nr there is not a voltageexceeding the predetermined level then active feedback circuit AFB doesnot electrically couple local collector line LCL and intermediate nodeNr together at least in alternate current. Herein, “in alternatecurrent” is used as compared to the fact that in the FIG. 5 activefeedback circuit AFB, local collector line LCL and intermediate node Nrare constantly, electrically coupled together via resistors Rfba1 andRfbb1 in direct current. More specifically for active feedback circuitAFB it is not until transistor cell Tra turns on that local collectorline LCL and intermediate node Nr are electrically connected together inalternate current.

[0139] A transistor cell receiving an intensive current generates heatand of active feedback circuits AFB 1-AFBm a corresponding AFBi has itsON voltage reduced, wherein i is a natural number corresponding to oneof one to m. As such, active feedback circuit AFBi in a transistor cellreceiving an intensive current and thus increased in temperature quicklyturns on if a load varies and a collector voltage is increased. As suchin response to the block of interest increasing in temperature alltransistor cells can be prevented from being further heated.

[0140] As can be seen from the FIG. 17 graph, a collapse regioncorresponds to a region with high collector-emitter voltage Vce. Assuch, by operating an active feedback circuit in the corresponding blockreceiving an intensive current and thus increased in collector voltage,in such a block the load curve can be prevented from expanding and thetransistor cell can thus be prevented from operating in the collapseregion.

[0141] Thus the transistor device can have a steady amplificationcharacteristic and it can also be free from destruction.

[0142]FIGS. 7A and 7B are each a circuit diagram showing the activefeedback circuit having another exemplary configuration.

[0143] With reference to FIG. 7A, active feedback circuit AFB can alsobe configured of k transistors Trd1-Trdk coupled in series between localcollector line LCL and intermediate node Nr, each in diode connection,wherein k represents a natural number.

[0144] If local collector line LCL and intermediate node Nr havetherebetween a voltage difference exceeding a predetermined level ofvoltage then the FIG. 7A active feedback circuit AFB electricallycouples local collector line LCL and intermediate node Nr together inalternate current to reduce the voltage on local collector line LCL. Ifthe voltage difference does not exceed the predetermined level ofvoltage then local collector line LCL and intermediate node Nr are notelectrically coupled together in alternate current.

[0145] In the FIG. 7A configuration the predetermined level of voltagecan be adjusted by the value of k and the value of a characteristic oftransistors Trd1-Trdk.

[0146] With reference to FIG. 7B, active feedback circuit AFB includestransistor cells Tra and Trd electrically coupled between localcollector line LCL and intermediate node Nr. Transistor cell Trd isprovided in diode connection. Active feedback circuit AFB also includesresistor Rfba coupled between local collector line LCL1 and transistorcell Tra1 at the base, and resistor Rfbb coupled between the base andemitter of transistor cell Tra1.

[0147] The FIG. 7B active feedback circuit AFB has a function similar tothat of the FIG. 7A active feedback circuit AFB. More specifically, iflocal collector line LCL and intermediate node Nr have therebetween avoltage difference exceeding a predetermined level of voltage then theFIG. 7B active feedback circuit AFB turns on to electrically couplelocal collector line LCL and intermediate node Nr together in alternatecurrent to reduce the voltage on local collector line LCL.

[0148] The FIG. 7B active feedback circuit AFB configuration correspondsto the FIG. 6 circuit configuration combined with the transistor cellprovided in diode connection that is used in FIG. 7A. As such, activefeedback circuit AFB can turn on at the predetermined level of voltagethat is adjusted by the ratio of resistors Rfba and Rfbb. Thus a smallernumber of transistor cells than in FIG. 7A can be used to configureactive feedback circuit AFB.

[0149]FIGS. 8 and 9 show first and second exemplary arrangements,respectively, of active feedback circuit AFB.

[0150] As shown in FIG. 8, blocks BLK1-BLKm are provided with theirrespective active feedback circuits AFB1-AFBm, each arranged in itsrespective block at a region susceptible to temperature elevation, i.e.,at a center portion.

[0151] With the active feedback circuits thus arranged, in a blockreceiving an intensive current attributed to temperature elevationactive feedback circuit AFB can have transistor cells Tra1-Tram havingan ON voltage reduced to allow active feedback circuit AFB to moreeffectively clamp a collector voltage.

[0152] As such if a load impedance varies and a load curve varies topass through a collapse region an active feedback circuit can be rapidlyoperated to prevent a transistor cell from operating in a collapseregion. Consequently, a power amplifier can be configured of atransistor device having a steady amplification characteristic and alsoprevented from destruction.

[0153]FIG. 9, as well as FIG. 3, shows blocks divided with a centerportion susceptible to temperature elevation serving as a boundary.Arranging active feedback circuit AFB in each divided block at a regionmore susceptible to heat elevation, i.e., at a center portion, canachieve an effect similar to that of FIG. 8.

[0154] First Variation of Third Embodiment

[0155] With reference to FIG. 10, a first variation of the thirdembodiment is different in that it has the configuration of the thirdembodiment as shown in FIG. 6 plus ballast resistors Rbb1-Rbbm providedfor blocks BLK1-BLKm, respectively. The remainder in configuration willnot be described as it is similar to FIG. 6.

[0156] Thus, ballast resistors Rbb1-Rbbm and active feedback circuitsAFB 1-AFBm together can reduce unevenness in base current betweenblocks. Thus, the both of the effects of the first and third embodimentscan be enjoyed to further prevent a specific transistor cell fromreceiving an intensive current, to provide a transistor device having afurther steadier amplification characteristic and further freer fromdestruction.

[0157] Second Variation of Third Embodiment

[0158] As shown in FIG. 11, the third embodiment in a second variationprovides a bipolar transistor device configured as described in thethird embodiment as shown in FIG. 6 with, as shown in FIG. 4, blocksBLK1-BLKm respectively provided with individual bias current supplycircuits 10-1 to 10-m and high impedance transmission lines RFC1-RFCm.

[0159] Thus, for a block receiving an intensive current, a bias currentsupply circuit correspondingly giving a feedback to a bias current andan active feedback circuit correspondingly reducing a collector voltage,together can reduce unevenness in base current between blocks. Thus theboth of the effects of the second and third embodiments can be enjoyedto provide a transistor device having a further steadier amplificationcharacteristic and further freer of destruction.

[0160] Third Variation of Third Embodiment

[0161] With reference to FIG. 12, the third embodiment in a thirdvariation provides a transistor device configured as described in thethird embodiment as shown in FIG. 6 plus bias current supply circuits11-1 to 11-m and ballast resistors Rbb1-Rbbm provided for blocksBLK1-BLKm, respectively, similarly as shown in the FIG. 5 configuration.

[0162] Thus, the effects of the variation of the second embodiment andthe third embodiment can be enjoyed to prevent a specific block fromreceiving an intensive current, to provide a transistor device having afurther steadier amplification characteristic and also further freerfrom destruction.

[0163] Fourth Embodiment

[0164]FIG. 13 is a conceptual view for illustrating an arrangement of atransistor device in a fourth embodiment of the present invention.

[0165]FIG. 13 shows an arrangement of transistors Q1-Q3 configuring theFIG. 1 power amplifier 1. Of the plurality of transistors configuringthe power amplifier and providing an amplification operation in phases,a transistor of a preceding stage is arranged in a region experiencing alarge temperature elevation, i.e., at a location closer to the center ofthe chip, and a transistor arranged at a succeeding stage is arranged ina region experiencing a small temperature elevation, i.e., at a locationcloser to a circumference of the chip. Thus the transistors of theplurality of stages are successively arranged, a preceding stagearranged at a region experiencing a large temperature elevation and asucceeding stage arranged at a region experiencing small temperatureelevation.

[0166] If a plurality of stages are used to amplify power in phases,succeeding transistors amplify larger levels of power and thus producemore heat. As such, such an arrangement as above allows a transistordevice amplifying a larger level of power and more readily generatingheat to be arranged at a region more readily dissipating heat, i.e., alocation closer to a circumference of the chip

[0167] As shown in FIG. 13, the first-stage transistor Q1 is configuredof a group of transistor cells arranged on a chip at the exact centerregion. A second-stage transistor Q2 is configured of a group oftransistor cells arranged at regions Q2 a and Q2 b closer thantransistor Q1 to the chip's circumference. The final-stage transistor Q3is configured of a group of transistor cells arranged at regions Q3 aand Q3 b located further closer to the chip's circumference.

[0168] In general when an HBT formed on a GaAs substrate is heated itaccordingly would be reduced in current-amplification rate β and hencein output voltage. Arranging a transistor device of a preceding stagecloser to the chip's center, which is susceptible to temperatureelevation, allows the first- and second-stage transistors Q1 and Q2 tohave an output power reduced as temperature increases.

[0169] As such, if temperature elevation causes intensive current, thefinal-stage transistor Q3, amplifying the highest level of power, canreceive a controlled, reduced power. As a result, transistor Q3 can befree of operation in a collapse region to provide a steady amplificationoperation and also allow each transistor cell to be free fromdestruction.

[0170] It should be noted that the FIG. 13 configuration of transistorcells arranged in regions Q1, Q2 a, Q2 b, Q3 a and Q3 b is applicable toany configuration in the first embodiment, the second embodiment and thevariation thereof, and the third embodiment and the first to thirdvariation thereof.

[0171] Furthermore the power amplifier can be formed of transistordevices provided in a number N other than three of stages to amplifypower in phases, wherein N represents a natural number. Of thetransistor devices arranged in N stages, a transistor device of aninitial stage can be arranged on a chip at the center, that of asucceeding stage can be arranged closer to the chip's circumference anda final-stage transistor device can be arranged at the chip'scircumference to obtain a similar effect.

[0172] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a plurality oftransistor cells divided and arranged in a plurality of blocks, forforming a bipolar transistor device; a plurality of first lines providedfor said plurality of blocks, respectively, and each electricallycoupled with a base region of each said transistor cell of acorresponding one of said blocks; a plurality of second lines providedfor said plurality of blocks, respectively, and each electricallycoupled with one of collector and emitter regions of each saidtransistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; and aplurality of bias current supply circuits provided for said plurality ofblocks, respectively, and each supplying a bias current to acorresponding one of said plurality of first lines, each said biascurrent supply circuit decreasing an amount of said bias current to besupplied, when said bias current has increased.
 2. The semiconductordevice according to claim 1, wherein each said bias current supplycircuit includes: a bias control transistor having a base regionreceiving a predetermined level of control voltage, electrically coupledbetween a power supply voltage for generating said bias current and anode supplying said bias current; and a bias adjusting portion providedto reduce a current drivability of said bias control transistor as saidbias current increases.
 3. The semiconductor device according to claim2, further comprising a plurality of radio-frequency attenuationportions provided for said plurality of blocks, respectively, and eachelectrically coupled between said node corresponding thereto and acorresponding one of said plurality of first lines, to attenuate aradio-frequency component of set bias current.
 4. The semiconductordevice according to claim 1, further comprising a plurality of ballastresistors provided for said plurality of blocks, respectively, and eachelectrically coupled between a corresponding one of said plurality ofbias supply circuits and a corresponding one of said plurality of firstlines, each said bias current supply circuit including a bias controltransistor having a base region receiving a predetermined level ofcontrol voltage, electrically coupled between a power supply voltage forgenerating said bias current and a corresponding one of said pluralityof ballast resistors.
 5. The semiconductor device according to claim 1,further comprising a plurality of feedback circuits provided for saidplurality of blocks, respectively, and each electrically coupling acorresponding one of a plurality of second lines and a predeterminedinternal node together if the corresponding one of said second lines andsaid internal node have therebetween a voltage difference exceeding apredetermined level of voltage.
 6. A semiconductor device comprising: aplurality of transistor cells divided and arranged in a plurality ofblocks, for forming a bipolar transistor device; a plurality of firstlines provided for said plurality of blocks, respectively, and eachelectrically coupled with a base region of each said transistor cell ofa corresponding one of said blocks; a plurality of second lines providedfor said plurality of blocks, respectively, and each electricallycoupled with one of collector and emitter regions of each saidtransistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; and aplurality of feedback circuits provided for said plurality of blocks,respectively, and each electrically coupling a corresponding one of aplurality of second lines and a predetermined internal node together ifthe corresponding one of said second lines and said internal node havetherebetween a voltage difference exceeding a predetermined level ofvoltage.
 7. The semiconductor device according to claim 6, wherein: saidplurality of feedback circuits each include a feedback transistorelectrically coupled between said corresponding second line and saidinternal node, and a voltage adjustment portion referring to a voltagedifference between said corresponding second line and said internal nodeto set a voltage difference between said internal node and a base regionof said feedback transistor, each said feedback circuit being arrangedin a corresponding one of said blocks at a location experiencing arelatively large heat elevation in operation.
 8. The semiconductordevice according to claim 7, wherein each said feedback circuit isarranged in a corresponding one of said blocks at a location close to acenter of said block.
 9. The semiconductor device according to claim 6,further comprising: a bias supply circuit shared by said plurality ofblocks and supplying each of said plurality of first lines with a biascurrent; and a plurality of ballast resistors provided for saidplurality of blocks, respectively, and each electrically coupled betweensaid bias supply circuit and a corresponding one of said plurality offirst lines.
 10. A semiconductor device provided on a semiconductorchip, comprising a plurality of bipolar transistor devices foramplifying a signal in phases, of said plurality of bipolar transistordevices said bipolar transistor device of a preceding stage beingarranged on said semiconductor chip at a location experiencing a largertemperature elevation than said bipolar transistors of any othersubsequent stages.
 11. The semiconductor device according to claim 10,wherein: of said plurality of bipolar transistor devices said bipolartransistor device of a preceding stage is arranged on said semiconductorchip closer to a center area than said bipolar transistors of any othersubsequent stages.
 12. The semiconductor device according to claim 10,wherein of said plurality of bipolar transistor devices at least onebipolar transistor device including a final stage each includes: aplurality of transistor cells divided and arranged in a plurality ofblocks, for forming said bipolar transistor device; a plurality of firstlines provided for said plurality of blocks, respectively, and eachelectrically coupled with a base region of each said transistor cell ofa corresponding one of said blocks; a plurality of second lines providedfor said plurality of blocks, respectively, and each electricallycoupled with one of collector and emitter regions of each saidtransistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; and aplurality of bias current supply circuits provided for said plurality ofblocks, respectively, and each supplying a bias current to acorresponding one of said plurality of first lines, each said biascurrent supply circuit decreasing an amount of said bias current to besupplied, when said bias current has increased.
 13. The semiconductordevice according to claim 12, wherein: said at least one bipolartransistor device each further includes a plurality of radio-frequencyattenuation portions provided for said plurality of blocks,respectively, and each electrically coupled between a corresponding oneof said plurality of bias supply circuits and a corresponding one ofsaid plurality of first lines, to attenuate a radio-frequency componentof set bias current; and each said bias current supply circuit has abias control transistor having a base region receiving a predeterminedlevel of control voltage, electrically coupled between a power supplyvoltage for generating said bias current and a corresponding one of aplurality of radio-frequency attenuation portions, and a bias adjustingportion provided to reduce a current drivability of said bias controltransistor as said bias current increases.
 14. The semiconductor deviceaccording to claim 12, wherein said at least one bipolar transistordevice each further includes a plurality of ballast resistors providedfor said plurality of blocks, respectively, and each electricallycoupled between a corresponding one of said plurality of bias supplycircuits and a corresponding one of said plurality of first lines, eachsaid bias current supply circuit having a bias control transistor with abase region receiving a predetermined level of control voltage,electrically coupled between a power supply voltage for generating saidbias current and a corresponding one of said plurality of ballastresistors.
 15. The semiconductor device according to claim 12, whereinsaid at least one bipolar transistor device each further includes aplurality of feedback circuits provided for said plurality of blocks,respectively, and each electrically coupling a corresponding one of aplurality of second lines and a predetermined internal node together ifthe corresponding one of said second lines and said internal node havetherebetween a voltage difference exceeding a predetermined level ofvoltage.
 16. The semiconductor device according to claim 10, wherein ofsaid plurality of bipolar transistor devices at least one said bipolartransistor device including said final stage each includes: a pluralityof transistor cells divided and arranged in a plurality of blocks, forforming said at least one bipolar transistor device; a plurality offirst lines provided for said plurality of blocks, respectively, andeach electrically coupled with a base region of each said transistorcell of a corresponding one of said blocks; a plurality of second linesprovided for said plurality of blocks, respectively, and eachelectrically coupled with one of collector and emitter regions of eachsaid transistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; and aplurality of feedback circuits provided for said plurality of blocks,respectively, and each electrically coupling a corresponding one of aplurality of second lines and a predetermined internal node together ifthe corresponding one of said second lines and said internal node havetherebetween a voltage difference exceeding a predetermined level ofvoltage.
 17. The semiconductor device according to claim 16, whereinsaid at least one bipolar transistor device each further includes: abias supply circuit shared by said plurality of blocks and supplyingeach of said plurality of first lines with a bias current; and aplurality of ballast resistors provided for said plurality of blocks,respectively, and each electrically coupled between said bias supplycircuit and a corresponding one of said plurality of first lines. 18.The semiconductor device according to claim 10, wherein of saidplurality of bipolar transistors at least one bipolar transistor deviceincluding said final stage each includes: a plurality of transistorcells divided and arranged in a plurality of blocks, for forming said atleast one bipolar transistor device; a plurality of first lines providedfor said plurality of blocks, respectively, and each electricallycoupled with a base region of each said transistor cell of acorresponding one of said blocks; a plurality of second lines providedfor said plurality of blocks, respectively, and each electricallycoupled with one of collector and emitter regions of each saidtransistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; a biassupply circuit shared by said plurality of blocks and supplying each ofsaid plurality of first lines with a bias current; and a plurality ofballast resistors provided for said plurality of blocks, respectively,and each electrically coupled between said bias supply circuit and acorresponding one of said plurality of first lines.
 19. A semiconductordevice provided on a semiconductor chip, comprising: a plurality oftransistor cells divided and arranged in a plurality of blocks, forforming a bipolar transistor device; a plurality of first lines providedfor said plurality of blocks, respectively, and each electricallycoupled with a base region of each said transistor cell of acorresponding one of said blocks; a plurality of second lines providedfor said plurality of blocks, respectively, and each electricallycoupled with one of collector and emitter regions of each saidtransistor cell of a corresponding one of said blocks; a referencevoltage line electrically coupled with the other of said collector andemitter regions of each of said plurality of transistor cells; a biassupply circuit shared by said plurality of blocks and supplying each ofsaid plurality of first lines with a bias current; and a plurality ofballast resistors provided for said plurality of blocks, respectively,and each electrically coupled between said bias supply circuit and acorresponding one of said plurality of first lines, said plurality ofballast resistors being arranged on said semiconductor chip at a regionexperiencing a greater temperature elevation than a region having saidplurality of transistor cells arranged therein.
 20. The semiconductordevice according to claim 19, wherein: said plurality of blocks arrangedin first and second directions in a matrix; and said plurality ofballast resistors are each arranged at a region located between acorresponding one of said plurality of blocks and another said blockadjacent to said corresponding one of said plurality of blocks in saidfirst direction.